Press
Press kit — F.A.R.C.E. Flash
| Tier | Price | Cap |
|---|---|---|
| Reader | $1 | uncapped |
| Single Lane | $34 | 100 |
| Founder's Array (8-lane) | $224 | 40 |
| Datacenter (24-lane) | $648 | 20 |
| Full Array (40-lane) | $1,074 | 10 |
| Bare Array (40-lane, media not included) | $315 | 25 |
| Validation Rig (40-lane, USB) | $1,450 | 5 |
| Host Interface Pack | $654 | 20 |
| Endurance Pack | $159 | 50 |
| Thermal Pack | $20 | 50 |
Boilerplate, 50 words
Farce Systems builds reference kits for memory-constrained machine learning. Its design, the F.A.R.C.E. Flash — Flash Array for Resource-Constrained Environments — attaches to a Linux computer the owner already has and presents 1.28 TB of system-addressable memory from a 40-lane array of consumer MicroSD cards. That is ten times the capacity of an NVIDIA DGX Spark, which is a complete machine; the kit is a peripheral and the host is not included in its price.
(49 words)
Boilerplate, 100 words
Farce Systems builds open reference kits for memory-constrained machine learning. Its first design, the F.A.R.C.E. Flash — Flash Array for Resource-Constrained Environments — attaches to a computer the owner already has and presents 1.28 TB of system-addressable memory from a 40-lane array — ten times the capacity of an NVIDIA DGX Spark, which is a complete machine where this is a peripheral.
That capacity comes from forty consumer MicroSD cards. Farce Systems ships reference kits, not products: every component is an off-the-shelf part with a public datasheet, and the PCB design, assembly guide, and OpenFARCE software are open source. Before designing the array, Farce Systems commissioned an independent feasibility analysis of a 128 GB configuration and published it unedited, conclusion included.
(100 words)
Four headlines
- Farce Systems Announces 1.28 TB Developer Kit, Ten Times the Memory of NVIDIA's DGX Spark
- This startup commissioned a study of its own product. The study says it won't work. They published it anyway.
- Forty cards, 240 traces, and a 64-day lifespan: inside the F.A.R.C.E. Flash
- Ten times the capacity, a twentieth of the speed: the F.A.R.C.E. Flash arrives
Fact sheet
| Product | F.A.R.C.E. Flash Developer Kit |
| Expansion | Flash Array for Resource-Constrained Environments |
| Company | Farce Systems |
| Tagline | Memory, at scale, at retail. |
| Secondary | 1.28 terabytes of system-addressable memory. Forty consumer MicroSD cards. One hand-soldered perfboard. |
| Software | OpenFARCE (open source, pre-alpha, not included in kits) |
| Community | Array Builders |
Architecture
| Fact | Value |
|---|---|
| Headline capacity, system-addressable | 1.28 TB |
| Capacity against the NVIDIA DGX Spark | 10x |
| Working set analysed by the Feasibility Report | 128 GB |
| Array size, reference design | 40 MicroSD slots |
| Card capacity shipped in kits | 32 GB, UHS-I, Class 10 |
| Raw array capacity, 40 x 32 GB | 1.28 TB |
| SDIO signals per card | 6 (CLK, CMD, DAT0-3) |
| Total high-speed traces, 40 cards | 240 |
| Trace spacing rule | 3W rule |
| Peak 3.3 V rail draw, 40 cards writing | ~6 A / ~20 W |
| Per-card write current | 100-150 mA |
Performance
| Fact | Value |
|---|---|
| Per-card UHS-I ceiling | 104 MB/s |
| Aggregate sequential read, 40 cards, ideal | ~4.1 GB/s |
| Projected decode speed | 1.5-3.0 tok/s |
| Projected TTFT at 32K context | 45-60 s |
| 70B model at 1.58-bit | ~13.8 GB |
| 70B model at 8-bit | ~70 GB |
| KV cache, 128K context, FP8 | ~20 GB |
Thermal and endurance
| Fact | Value |
|---|---|
| Thermal throttle threshold | 70-85 °C |
| Throttled speed | <10 MB/s |
| Consumer card P/E cycles | 1,000-3,000 |
| pSLC card P/E cycles | up to 60,000 |
| Assumed WAF under LLM load | 5.0 conservative, 10.0+ realistic |
| Array lifespan under continuous load | ~64 days |
Reference: NVIDIA DGX Spark
| Fact | Value |
|---|---|
| Price | $4,700 |
| Memory | 128 GB unified |
| Bandwidth | >500 GB/s |
| 70B 8-bit decode | 40-60 tok/s |
The NVIDIA DGX Spark is a product of NVIDIA Corporation. Farce Systems has no affiliation with NVIDIA.
Kits
No kit contains a fabricated PCB, an enclosure, assembled hardware, or software. Full contents lists are published per tier.
Report
Feasibility Analysis of MicroSD-Backed LLM Inference Architectures. Commissioned by Farce Systems, published unedited, including its conclusion that the architecture is impractical. Prepared with AI research tooling; reviewed for consistency, not corrected.
Full text, with section anchors, at /farce-flash/report/.
Quotable, verbatim:
a monument to the lengths to which engineers will go to avoid purchasing enterprise hardware
It is functionally the equivalent of watching a human type.
machine learning can indeed run in a flash
Assets
Wordmark, icon, board renders, architecture diagrams, and 1200x630 social cards: /farce-flash/press/
Contact
hello@jhickson.us