F.A.R.C.E. Flash

In 2026, memory is the constraint. Demand for long-context reasoning and agentic workloads has pulled DRAM and NAND supply toward the datacenter, and the price per gigabyte has followed. The effect on independent researchers has been direct.

The industry's answer for local inference is the NVIDIA DGX Spark. It is an excellent machine. It provides 128 GB of unified memory with over 500 GB/s of bandwidth, and it runs a 70-billion parameter model without complaint. It also costs $4,700.

We respect that machine. We could not afford one, and neither could most of the people we build for, so we set out to match it. We overshot.

Every inference workload has the same shape. A large body of weights, a key-value cache that grows with context, and a memory system that cannot hold both. The industry solves this by buying faster memory.

We looked at the other end of the table. Per gigabyte, the cheapest solid-state storage on the open market is not enterprise NVMe. It is the consumer MicroSD card — sold in forty-packs, stocked in every electronics aisle on earth, manufactured at a scale no enterprise part will ever reach.

We asked a simple question. What if you bought enough of them?

Forty cards at thirty-two gigabytes is 1.28 TB. We noticed this after we had already designed the board.

The reference design is a 40-lane parallel SDIO array.

Forty independent buses. Each MicroSD socket gets its own SDIO interface, running 4-bit UHS-I at a 208 MHz clock. Six signals per card: clock, command, and four data lines. Nothing is shared, so nothing arbitrates.

240 high-speed traces, routed to spec. Forty cards times six signals is 240 traces that must reach the controller with their eye diagrams intact. The layout follows the 3W rule — adjacent traces separated by at least three times a single trace width — on signal layers backed by unbroken ground planes one dielectric away, with ground transition vias placed beside every signal via. Signal-integrity-forward, from the first revision.

Multiphase power delivery. Forty cards writing at once draw roughly 6 A on the 3.3 V rail, near 20 W for storage media alone. A single-phase converter droops under that load step, and a MicroSD controller that sees 3.3 V sag toward 2.7 V will brown-out reset mid-write. The reference design specifies a multiphase DC-DC converter that divides the load across timed power stages. Power-dense by design.

Local bulk capacitance. Every socket gets its own bank of multi-layer ceramic capacitors, placed adjacent to the card. Low ESR, low ESL, and close enough to answer a load step before the regulator has noticed one.

A MicroSD card puts a controller and several stacked NAND dies inside a 15 x 11 x 1 mm plastic shell. Plastic insulates. Under continuous I/O the die reaches its throttle threshold — 70 to 85 °C — and the controller drops a 104 MB/s card below 10 MB/s to protect itself.

The reference design specifies a direct-die thermal solution, applied by the builder. Sand the casing back to expose the die, apply thermal interface material, clamp the array under a finned aluminum heatsink, and move air across it. The procedure is documented and the abrasives are included.

The Linux kernel does not accept that an array of removable SD cards is memory. Standard mmap() with swap on a high-latency block device produces swap thrashing: the kernel spends its cycles shuffling 4 KB pages, and token generation stops.

OpenFARCE bypasses legacy kernel assumptions. It is a user-space I/O layer. It locks the resident model with --mlock so the kernel cannot page it out, skips the VFS entirely, and issues asynchronous scatter-gather reads against the raw block devices. It reads the attention pattern to predict which KV blocks the next decode step will need, and prefetches them while the current token is still computing.

OpenFARCE is open source. Status: pre-alpha. It is not included in any kit.

This is why it works.

BitNet-class ternary quantization restricts every weight to one of three discrete values. At 1.58 bits per weight, a 70-billion parameter model compresses from a native footprint near 140 GB to approximately 13.8 GB, holding near-parity with full-precision models on perplexity.

That number changes the architecture. 13.8 GB of weights fit in the DRAM of a budget developer board, which means the weights never stream from the array during decode. The array stops trying to be memory and becomes what it is actually good at — a large, sequential sink for KV cache, written in contiguous 256-token chunks.

That reframes what the capacity is for. Measured as history rather than as weights, the array holds roughly 7.7 million tokens of context. How much of that is usable at a speed you would tolerate is a different number, and a much smaller one. We work it out in full on the comparison page.

We wrote the software first. Neither array exists yet.

OpenFARCE is published and complete enough to read: it enumerates USB-attached readers by physical topology, brings them up in stages so the hub does not brown out, assembles them into a RAID 0 span, presents that span to the kernel as swap, benchmarks it, and keeps a ledger of how fast the media is wearing out.

What gets built first is not the array. It is eight 16 GB cards in eight USB readers on one powered hub, attached to a Raspberry Pi 4B. Eight lanes, 128 GB raw — a figure that matches the DGX Spark's 128 GB exactly, by arithmetic coincidence, and says nothing whatever about speed.

The parts cost about $70. We have not bought them.

Eight lanes is not forty. No measurement taken on eight will be presented as a measurement of forty, and every figure the rig produces will carry the lane count it was measured on. Until then every array figure on this page is the Feasibility Report's projection and is labelled as one.

The Feasibility Report analyzes a 128 GB configuration. We consider its findings conservative.

Our analysis evaluated three offloading configurations against the SDIO array. Two are marked Impossible. The third — 1.58-bit weights, with the array carrying KV cache only — is marked:

We publish our unflinching third-party analysis unedited, including its conclusion.

Consumable media architecture.

Consumer MicroSD cards are rated for 1,000 to 3,000 program/erase cycles. Under the fragmented write pattern of a swapping inference engine, the write amplification factor climbs to 10.0 or higher — every gigabyte of KV cache written costs ten gigabytes of endurance. Our analysis models a 64-card configuration study and projects that an array under continuous load exhausts itself in approximately 64 days.

We plan for that rather than around it. Media is a consumable in this architecture, the same way it is in a tape library. The Endurance Pack ships replacement cards.

The Feasibility Report models a 64-card configuration. Ours is forty. We are measuring what that does to the projection.

Add-ons

• 100 backersOpenFARCE assembly video
• 250 backersThe 40-lane array: Farce Systems builds the full array on a desktop host, benchmarks it, and publishes the numbers whatever they say
• 500 backersCommunity Discord
• 1,000 backersSecond color of sticker

What you receive. Parts. The contents lists above are complete and exact — breakout boards, perfboard, wire, passives, a heatsink, cards. There is no printed circuit board in any kit, and we do not sell one. Where this page says "the reference design," it means published files, not an object. There is no enclosure and no firmware on a chip. You build the board on perfboard yourself.

Parts sourcing. Every item is a commodity part with a public datasheet. MicroSD prices moved roughly 30% month to month through 2026 and will move again. If a tier's parts cost rises past 70% of its price, we pause that tier rather than ship a thinner kit. If a tier becomes unfulfillable, we offer refunds before ordering anything.

Firmware timeline. OpenFARCE is pre-alpha and is not included in any kit. Nothing you receive will run a language model on arrival, and we will not give a date when it will.

The array is not expected to survive ninety days of continuous load. The analysis projects approximately 64. That is the finding. We have not disputed it and we have not designed around it.

What "system-addressable" means. The array is exposed to the operating system as swap-backed block storage over USB. It is not RAM and does not perform like RAM.

Heat, power and fire. The Validation Rig ships four 12 V 4 A supplies — around 192 W — intended to run continuously for months. Forty cards at full duty cycle get hot enough to throttle, which means hot enough to matter. Run it on a hard surface with air around it, not in a cupboard or on carpet, and put a smoke detector in the room. The fire-resistant document bag in the 40-lane tiers is a real precaution and is listed because it is one.

The direct-die procedure is destructive and optional. Sanding a card's casing away to expose the die voids its warranty, produces plastic dust, and ruins cards when it goes wrong. It is a documented procedure, not a requirement, and nothing else in the kit depends on it. Wear eye protection or skip it.

Scale. One person packs and ships these from a fixed parts budget. Every physical tier is capped for that reason, and a capped-out tier closes.

Farce Systems is two engineers — one hardware, one systems — working from the position that the memory wall is an economic problem before it is a physical one.

We commissioned the feasibility analysis after the board was designed, and published what came back. The kits are priced against a public bill of materials.

Farce Systems is a project, not a corporation.